1. Field of the Invention
The present invention relates to computer systems. Specifically, the present invention relates to the configuration and control of signals used to access input/output (I/O) mapped computer system resources.
2. Related Art
Many computers use a technique for mapping various portions of a system memory map to various system resources. Such computer system resources include expansion memory boards and/or network interface logic. Two main types of mapping schemes may exist in these systems: a memory mapping scheme, or; an input/output (I/O) mapping technique.
In a memory mapped system, a particular system resource may be accessed by applying a predetermined system address or one of a range of system addresses to a computer system bus during memory access cycles.
In an I/O mapped system, a particular system resource may be accessed when a system address or one of a range of system addresses is applied to the computer system bus during an I/O cycle. In I/O mapped systems, at least one control signal is typically provided for signaling the completion of a resource access request. Such a control signal is often denoted the input/output (I/O) channel ready (IOCHRDY) signal. In some systems, an I/O access cycle time must be extended using the IOCHRDY signal to allow time for the addressed system resource to respond. Most computer systems using an IOCHRDY signal require the IOCHRDY signal to transition from a high state to a low state shortly after a command strobe (i.e., an I/O read (IORD) signal or an I/O write (IOWR) signal) becomes active. If this occurs, the access cycle length will be extended until the IOCHRDY signal is deactivated. Other computer systems, however, will not reliably extend the memory access cycle time unless the IOCHRDY signal transitions from a high state to a low state at least 15 nanoseconds before the command strobe (IORD/IOWR) becomes active. Systems requiring the active IOCHRDY signal prior to the command strobe (IORD/IOWR) are often called early IOCHRDY systems. Other systems not requiring an early IOCHRDY signal are often called normal IOCHRDY systems or sometimes late IOCHRDY systems.
In order to accommodate both types of IOCHRDY implementations (i.e., the early IOCHRDY implementation and the late IOCHRDY implementation), prior art systems employ the use of hardware jumpers or other hardware means for defining a point of time in the resource access cycle when the IOCHRDY transitions to an active state. Unfortunately, the use of jumpers in this manner leads to many problems. If a system resource circuit board is configured incorrectly, corrupted data and/or system crashes may result. Moreover, an improperly configured jumper corresponding to an IOCHRDY implementation may be very difficult to detect. Even though the computer system will clearly be acting improperly, it will not be clear that the sequencing of the IOCHRDY signal is the source of the problem.
Thus, a better means for configuring and controlling the operation of computer system resource addressing control signals is needed.